Improved Subthreshold Characteristics by Back-Gate Coupling on Ferroelectric ETSOI FETs

In this work, extremely thin silicon-on-insulator field effective transistors (ETSOI FETs) are fabricated with an ultra-thin 3 nm ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer. Furthermore, the subthreshold characteristics of the devices with double gate modulation are investigated extensively. Contributing to the advantages of the back-gate voltage coupling effects, the minimum subthreshold swing (SS) value of a 40 nm ETSOI device could be adjusted from the initial 80.8–50 mV/dec, which shows ultra-steep SS characteristics. To illustrate this electrical character, a simple analytical model based on the transient Miller model is demonstrated. This work shows the feasibility of FE ETSOI FET for ultra-low-power applications with dynamic threshold adjustment.


Background
To fabricate an ultra-low-power CMOS integrated circuits, many researches have investigated field effect transistors (FETs) with new structures [1][2][3] or revolutionary principles [4,5]. Extremely thin silicon-on-insulator (ETSOI) FETs, which have improved the gate control ability and reduced the leakage by the fully depleted channel and bottom isolation, respectively, are proposed to realize ultra-low-power-consumption circuits [6][7][8][9][10][11][12][13][14][15]. However, the devices cannot break the limitations of "Boltzmann tyranny" only by structural innovation. Ferroelectric ETSOI FETs (FE ETSOI FET), which integrate a ferroelectric (FE) film into the gate stacks, could realize the amplification of the surface voltage on the channel and achieve super-steep SSs (< 60 mV/dec) [16][17][18]. In the past several years, the improved subthreshold characteristics of the FE ETSOI FETs were reported [19,20]. Although the subthreshold characteristics could be improved, there are few works revealing the back-gate coupling effect on the performances of the FE devices.
In this work, ETSOI FETs are fabricated with an ultra-thin 3-nm-thick FE hafnium zirconium oxides (Hf 0.5 Zr 0.5 O 2 ) film. Based on the advantages of double gate structure of the devices, a method for improving the subthreshold characteristics of FE ETSOI FETs by backgate voltage coupling is demonstrated. The values of the subthreshold swing (SS) could be adjusted from 80.8 to 50 mV/dec by the back-gate voltage modulating for a 40 nm physical gate length (L G ) ETSOI device, which shows obvious ultra-steep SS characteristics. To illustrate this electrical character, a simple analytical model based on the transient Miller model is used in this work.

Method
Devices were fabricated on SOI wafers with a buried oxide (BOX) thickness of 145 nm. A process fabrication flow of the ETSOI MOSFET is depicted in Fig. 1a  to 7 nm by thermal oxidation followed by diluted hydrofluoric acid. Dummy poly gates were formed followed by ultra-thin spacers (∼8 nm). Faced raised source and drain (RSD) was epi-grown with in situ doped boron ions. In order to form high-quality raised SiGe SD, the thickness of silicon loss in SD area needs to be carefully controlled. In the flowing steps, an additional implantation of As and a rapid thermal anneal (RTA) process was performed to drive in the doped ions to form the extensions. After self-allied silicide formation, dummy poly gates were removed. In the flowing steps, after the ~ 1 nm SiO2 interfacial layer (IL) formation by chemical O 3 oxidation, a sequential deposition of multilayer Hf 0.5 Zr 0.5 O 2 and TiN films was performed by an atomic layer deposition (ALD) and chemical vapor deposition (CVD) process, respectively, where the FE Hf 0.5 Zr 0.5 O 2 material replaced the conventional HfO 2 film. The Hf 0.5 Zr 0.5 O 2 film (3 nm) was deposited by ALD at 300 °C using Hf (TEMAH) and Zr (TEMAZ)-based organic precursors. A RTA process of 550 °C/30 s at nitrogen atmosphere was carried out after the deposition of Hf 0.5 Zr 0.5 O 2 , which was also helpful to improve the quality of the Hf 0.5 Zr 0.5 O 2 film. The SD metal contact by the W-plug and the alloy processes by forming gas annealing (FGA) at 450 °C/30 min were carried out in the subsequent steps. The cross-sectional profiles of FE ETSOI FET were observed using a cross-sectional transmission electron microscope (TEM). The electrical characterization was performed using Keithley 4200 and Agilent 4156C semiconductor parameter analyzers.  Figure 1b shows the cross-sectional TEM image of a 40-nm L G device. High-κ metal gates (HKMGs) multilayers, W/3-nm TiN/3-nm HZO/1-nm SiO (IL), are shown in Fig. 1c. In this figure, multilayer HKMGs distributed on the channel are highly conformal and uniform. The thicknesses of the IL and FE layers, labeled in Fig. 1c, are about 1 nm and 3 nm, respectively, and the ultra-thin Si channel layer is 7 nm in thickness, which contributes to better control of the short channel effects (SCEs) than that of bulk MOSFET. Figure 1d-g show the elements distribution of the FE device. It can be seen that Hf and Zr atoms are basically concentrated in the medium layer, and there is no diffusion for multilayer materials. The above results show that the process controls appropriate during manufacturing process of the device, and the Hf 0.5 Zr 0.5 O 2 has good process compatibility with the conventional CMOS fabrication.

Result and Discussion
Furthermore, to confirm the ferroelectricity of the HZO film, capacitors with TiN /3-nm HZO/ ~ 1-nm SiO 2 /Si were fabricated, which own similarly conditions with the devices, and analyzed by piezoresponse force microscopy (PFM) test using Asylum MFP-3D. Figure 1h and i show corresponding results for the characterization with a typical frequency range ~ 350-400 kHz. The presence of square 180° hysteresis in PFM phase indicates the upward and downward polarization states, and butterflyshaped loops in PFM amplitude implies robust remanent polarization for the FE film. Figure 2a shows the transfer curves (I DS -V GS ) of a 40-nm L G FE ETSOI FETs at V DS s of 50 and 900 mV, respectively. The calculated value of the drain-induced barrier lowering (DIBL) is ~ 130 mV/V indicating serious SCEs. In addition, Fig. 2b summarizes the corresponding variations of SSs as a function of V GS for the devices. The results show that the minimum value of the SS is higher than 82 mV/dec, which is much higher the limit value of "Boltzmann tyranny. " In order to improve the SCEs, based on the advantages of double gate structure of the devices, a method for enhancing the subthreshold characteristics by backgate voltage coupling effects is demonstrated and analyzed, subsequently. The I DS -V GS of a 40-nm L G device at V DS = 50 mV (V DS@LIN ) and 900 mV (V DS@SAT ) with various bias gate voltages (V SUB ) from −35 to 35 V are shown in Fig. 3a and b, respectively. When the value of V SUB bias is positive, there is an obvious shoulder near I DS = 10 -8 A. But when the value of V SUB bias is changed to negative, the shoulder disappears. This indicates that the back channel of the device has a parasitic device which is also controlled by V GS . The positive bias will enhance the parasitic effect, while the negative bias can turn off the parasitic effect. Figure 3c summarizes the corresponding variations of threshold voltage (V T s) and factors of DIBLs as a function of V SUB s for the device shown in Fig. 3a. All of the corresponding V T values are extracted at a fixed normalized I DS of 10 nA/μm. It can be seen that both V T@LIN and V T@ SAT increase linearly with V SUB changing from positive to negative. With different bias of the V SUB , the V T can be tuned within the range of almost 1.5 V. It demonstrates V SUB bias can be effectively served as a method to modulate ETSOI device characteristics due to the controlling of carrier confinement. Furthermore, it is worth noting that with the decrease of V SUB , the difference between V T@LIN and V T@SAT tends to decrease gradually, which means smaller values of the DIBLs and the improved SCEs.
With V SUB value decreasing continuously, the value of V T@LIN -V T @SAT shows a decrease tendency and changed from positive under + V SUB to negative under some -V SUB value, which indicates the phenomenon of the negative DIBL (N-DIBL). With various V SUB bias, the behaviors of SCEs are different. For positive V SUB bias, currieries were pulled away from top channel, and thus, DIBL gets worse. Besides, for negative V SUB bias, top gate controllability of channel carriers was enhanced, thereby achieving better DIBL performance. Furthermore, the random variation of DIBLs, especially for those negative DIBLs, may be caused by the transit negative capacitance phenomenon induced by the HZO film in the gate stacks [21]. In addition, Fig. 3d summarizes the corresponding variations of SSs as a function of V DS for the devices. Corresponding to the above results, with the decrease of V SUB , the values of SSs show a decreasing trend and the minimum SS value of the device reaches 50 mV/dec at V DS = 50 mV and V SUB = − 35 V, which is far below the limit of 60 mV/dec for the conventional FETs and exhibiting the great advantage for ultra-low-power application. Due to the shoulder To illustrate the mechanism of the substrate voltage enhancing SCEs of FE ETSOI FET, a simple analytical model based on ferroelectric domain switching is used shown in Fig. 4. Figure 4a shows capacitance coupling in fabricated FE ETSOI FET, where C FE , C DE , C CHAN and C BOX are capacitance of FE film, silicon oxide dielectric layer, silicon channel and box silicon oxide, respectively. C MOS can be written as ( ). According to the transient Miller model [22,23], the equivalent circuit model of this DE-FE network is shown in Fig. 4b   This equation suggests that the increase in C FE with V CFE is the prime factor for the ultra-steep SS characteristics, which must be sufficiently large. The discussion in this work assumes that τ, dC FE /dt and dV CFE /dV GS are not affected by V SUB changing, so we can conclude from the equation that ultra-steep SS will be easier to meet with decrease in C MOS .
For the fabricated FE ETSOI MOSFET, as V SUB increases, the energy band of the channel gradually bends, that is to say, more electrons could fill the channel. Due to the charge shielding effects of the filled electrons, the C MOS value gradually increases. As Fig. 4c shown, with a low C MOS value, the inequality is easier to establish, and thus, the ultra-steep SSs are more easily to be obtained [22].

Conclusion
In this work, an innovative way to enhance the subthreshold characteristics effects by coupling back-gate voltage is proposed and realized initially with FE ETSOI MOSFETs. The minimum SS value of a 40 nm ETSOI device could be adjusted from the initial 80.8 to 50 mV/dec, which shows ultra-steep SS characteristics. A simple analytical model based on the transient Miller model is used in this work to illustrate the mechanism. This work demonstrates the feasibility of FE ETSOI MOSFET in ultra-low-power application with dynamic threshold adjustment.